The Receiver Loss of Signal (RxLOS) signal is an output of the analog signal detection circuit in a typical serializer/deserializer (SerDes) device core that indicates loss of signal at the SerDes receiver. The RxLOS signal may either switch between logic-one and logic-zero for a short period or remain at either value for an extended period. Active glitches may lead to indicating an erroneous loss of signal condition or erroneous recovery of a lost signal. Input signals affected by inter-symbol interference or channel noise may complicate returning an accurate loss of signal. Correction or calibration of offset error in the RxLOS signal is therefore common.
Offset calibration is generally performed in the peak detector (PKDET) cell of the RxLOS circuit. When the RxLOS circuit is in operating mode, the PKDET cell provides input to a comparator. The PKDET cell compares the received peak voltage with a known reference voltage (ex.—threshold voltage) and the comparator makes a decision (logic-zero or logic-one) with respect to the calibrated signal. The offset of the PKDET cell will affect the decision made by the comparator. It may therefore be desirable to provide improved signal offset calibration while conserving space by utilizing a more compact and cost-efficient circuit.